Maan Dhirendra Jain , Priyanshu Soni

Reducing power consumption is an indispensable quest in our modern world. With the ever-present need for portable devices like smartphones and laptops, minimizing energy usage dissipation has become a central challenge. This pressing concern has driven the development of innovative techniques to curb power loss in Very-Large-Scale Integration (VLSI) chips, the workhorses of modern electronics. While CMOS technology offers scaling advantages and inherently low static power dissipation, challenges persist. Despite significant increases in transistor count and operating frequency, modern processors grapple with leakage currents similar to their decade-old counterparts. Understanding the various power dissipation mechanisms However, the pursuit of ever-smaller, faster, and lower-power chips necessitates a delicate balancing act between power consumption, performance, and chip area. This paper explores the multifaceted problem of power dissipation in CMOS circuits, delving into both dynamic and static power sources . This review underscores the critical role of low-power design in shaping the future of VLSI technology.

https://doi.org/10.58357/jedcs.2024.v3.i2.12